1. Field of the Invention
The present invention relates to a digital-to-analog converter (called hereinafter "DAC") and, more particularly, to an improvement in conversion precision of the DAC.
2. Description of the Related Art
As the bit resolution required to a DAC becomes severe, the DAC becomes more complicated and expensive. Therefore, in a digital audio field particularly, an over-sampling technique has been employed as well-known in the art to obtain a high bit resolution and to reproduce an analog signal by using a DAC of low bit resolution. For example, in a case where a 16-bit resolution is required at a conversion rate of f.sub.1, if the audio signal is over-sampled to be converted into a two-bit digital signal at a conversion rate of f.sub.2 that is 128 times as large as f.sub.1, f.sub.2 =128.times.f.sub.1, the digital signal can be reproduced as the analog audio signal equivalent to that converted from the 16-bit resolusion digital signal. More specifically the over-sampled two-bit digital signal is converted into an analog, signal by two-bit DAC and then being subjected to a low-pass filter.
Referring to FIG. 1, there is shown a 2-bit DAC suitable for converting the over-sampled two-bit digital signal into an analog signal. The two-bit digital data GD having first and second bits D.sub.0 and D.sub.1 is supplied to a set of input terminals 1-1 and 1-2 at a rate that is equal to the clock rate of a clock signal CK but advances in phase by a half cycle period of the clock signal CK. The input terminals 1-1 and 1-2 are connected to a decoder 2 which decodes the digital data GD to produce decoded data DD.sub.0 to DD.sub.2 as shown in TABLE below.
TABLE ______________________________________ D.sub.0 D.sub.1 DD.sub.0 DD.sub.1 DD.sub.2 ______________________________________ 0 0 0 0 0 1 0 1 0 0 0 1 1 1 0 1 1 1 1 1 ______________________________________
The decoded data DD.sub.0 to DD.sub.2 are supplied to data terminals D of flip-flops (FFs) 5 to 7, respectively. These FFs 5 to 7 latch the decoded data DD.sub.0 to DD.sub.2 supplied thereto in synchronism with the leading edge of the clock signal CK supplied to clock terminals .phi. thereof. When each of the FFs 5 to 7 latches the corresponding decoded data DD of "1", it produces a predetermined constant voltage (or current) of the same value at its Q output terminal. On the other hand, each of the FFs 5 to 7 produces zero voltage (or current) when it latches the decoded data of "0". The outputs derived from the FFs 5 to 7 are added with each other by an adder 8 and the added result is derived via an output terminal 9 as an analog signal A. Thus, the digital data GD is converted into the analog signal A whose voltage (or current) value (or amplitude) is changed in accordance with the numeral represented by the digital data GD.
However, the DAC shown in FIG. 1 has a disadvantage that the conversion precision is interior. More specifically, when the decoded data DD changes from "0" to "1", the output of the corresponding FF 5, 6 or 7 raises from zero voltage (current) to the predetermined voltage (current) value. On the other hand, the output of the FF 5, 6 or 7 falls from the predetermined voltage (current) value to zero voltage (current) in response to the change of the decoded data DD from "1" to "0". As well known in the art, the raising speed of the output of the FF is not equal to the falling speed thereof. For example, as the output waveform of the FF 7 is shown in FIG. 2, the output of the FF 7 raises up to the predetermined voltage (current) value VA at a relatively slow speed, whereas falls down to zero voltage (current) immediately. For this reason, the integrated value of the output from the FF 7 obtained during one clock period when the decode data DD.sub.2 of the same logic level appears first is not coincident with that during one clock period when the decoded data DD.sub.2 of the same logic level appears successively, as apparent from the comparison between periodes T.sub.1 and T.sub.2 or T.sub.3 and T.sub.4 shown in FIG. 2.